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Semiconductor

SMIC-JCET Strategic Cooperation on Wafer Bumping and Its Effects on the Global Semiconductor Industry

April 29, 2014 / Yaru Shih

13 Page, Topical Report

US$880 (Single User License)

Abstract

In the wake of the declaration made by China's government to make efforts to build an indigenous semiconductor industry in February 2014, SMIC (Semiconductor Manufacturing International Corporation) - China's leading wafer foundry - and JCET (Jiangsu Changjiang Electronics Technology Co.) - the leading packaging service provider in China - announced that they will jointly build an 12" bumping and testing facility, in which SMIC and JCET holds 51% and 49% stake, respectively. This report points out the reasons behind the SMIC-JCET cooperation and provides in-depth analysis of China's rise and the consequences thereof for the global semiconductor industry.

List of Topics
1. Background
2. Bumping a Key for Improved Wafer Yields of Advanced IC Manufacturing Technologies
2.1 SMIC Still Centers on 0.15/0.18nm and Its Advanced Manufacturing Process Share Remains Slim
2.2 TSMC's 40/45nm Wafer Share Topped Over 50%
2.3 Wafer Bumping Technology as an Indicator to Prove Advanced Packaging Capabilities
2.4 IC Manufacturers and Packaging Service Providers to Ramp Up Bumping Capacity
3. Reasons and Factors behind the Cooperation
3.1 Wafer-bumping to Help SMIC Increase Mass Production Speed
3.2 Cooperation to Reduce Risks Associated with Wafer Bumping
4. Conclusion
4.1 SMIC-JCET Cooperation Take Aims at Chinese Government Funding
4.2 The Cooperation Might Make a Stir on Market Landscape of High-end IC Manfuacturing
Appendix

List of Figures
Figue 1 SMIC Revenue Share by Process Technology, 1Q 2011 - 4Q 2013
Figue 2 TSMC Revenue Share by Process Technology, 1Q 2011 - 4Q 2013

List of Tables
Table 1 Chinese Indigenous IC Foundries and News
Table 2 Chinese Wafer Bumping Patent Applicants and Holders

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